Memory cells are circuits wherein information may be stored in a low current stand-by mode and may be written or read in a higher current mode. This current difference is referred to as dynamic range. A predetermined number of cells are located in a row between each of a plurality of upper and lower word lines and another predetermined number of cells are located in a column between a plurality of bit lines. In other words, each cell is uniquely coupled between a combination of word lines and bit lines.
Typically, a row of cells is selected when increased voltage is supplied to the upper word line. A particular cell in that row is read by a sense amplifier coupled to the bit lines. A first read current through one bit line flows directly to the sense amplifier. A second read current through the other bit line flows through one side of the memory cell to the upper word line. When a cell is written, the first read current is directed through the cell and the second read current is directed to the sense amplifier.
Access time refers to the time required to raise the voltage on the upper word line of a selected row of cells. This must be accomplished before the write signal causes current to flow through the appropriate bit line to write the cell. As memories are manufactured with more cells within the array, either a larger current, i.e., higher power dissipation, is required to hold the deselected row down or a larger load resistor, i.e., slower access time, is needed.
One convential memory cell comprises a cross-coupled pair of multi-emitter NPN transistors operating as a latch. Each multi-emitter NPN transistor has a first emitter connected to a lower word line, and a second emitter connected to a first and second bit line, respectively. The collector of each are coupled to an upper word line by a first and second resistive load, respectively. This resistive load, for instance, comprises a resistor and a Schottky diode in parallel. This Schottky-clamped resistor load arrangement is used to implement the non-linear resistance required to maintain reasonable cell differential voltage under both the low current stand-by mode and the higher current read/write mode. Cell differential voltage is designed at typically 350 millivolts during standby and provides sufficient noise immunity. This differential voltage is usually obtained with a large resistor of approximately 30K ohms. However, this passive load requires a relative high current in the standby mode. Furthermore, the transistors of this cell can be saturated which results in a large storage charge in the cell.
Another conventional memory cell comprises a cross coupled pair of NPN transistor operated in the inverse mode. An emitter of each is connected to a lower word line, a collector is connected to each other's base and to the collector of a first and second PNP load transistor, respectively. First and second sense transistors have their bases connected to the base of a respective one of the cross-coupled pair, their collectors connected to the collectors of the first and second PNP load transistors, respectively, and their emitters connected to a first and second bit line, respectively. The emitters and bases of the PNP load transistors are connected to an upper word line and the lower word line, respectively. A problem existing with this cell is that the respective multi-emitter transistor and load transistor will saturate in the "on" state, resulting in a large storage charge within the memory cell. This causes the cell to respond slowly to a write current.
Another previously known cell, typically called an SCR cell, comprises cross-coupled first and second multi-emitter NPN transistors, each having a first emitter connected to a lower word line, and a second emitter connected to a first and second bit line, respectively. The collector of the first cross-coupled multi-emitter NPN transistor is connected to the base of the second cross-coupled multi-emitter NPN transistor, and is connected to the base and collector of a first and second PNP load transistor, respectively. The collector of the second cross-coupled multi-emitter NPN transistor is connected to the base of the first cross-coupled multi-emitter NPN transistor, and is connected to the base and collector of the second and first PNP load transistor, respectively. The emitters of the PNP load transistors are connected to an upper word line. A problem existing with this cell, as with the previously described cell, is that the respective multi-emitter transistor and load transistor will saturate in the "on" state, resulting in large storage charge. This causes the cell to respond slowly to a write current.
Another conventional memory cell comprises cross-coupled first and second NPN transistors operated in the inverse mode. An emitter of each is connected to a lower word line and a collector is connected to the other's base and to the collector of a first and second PNP load transistor, respectively. A third and fourth NPN transistor each have their emitters connected to a first and second bit line, respectively, a base connected to the base of the first and second NPN transistors, respectively, and a collector connected together and to the bases of first and second PNP load transistors. The emitters of the PNP load transistors are coupled to an upper word line. A problem existing with this cell is that a write current supplied to the emitter of either the third or fourth NPN transistor adds to the base current of the first or second NPN transistor, respectively. This base current is beta multiplied by the PNP transistor, which sources current into the respective third or fourth NPN transistor which is trying to be turned off. This creates a SCR situation in which the cell may not write.
All of the above previously known memory cells have certain characteristics giving it an advantage over another. However, all of these previously known memory cells have a fundamental charge storage problem caused by large read/write currents flowing in the clamping diode of a resistor loaded cell and the injector of a PNP load cell. This charge storage results in long write pulse width and long write recovery times for these cells.
Therefore, a memory cell is needed having small read and write times and a large current dynamic range in which the large bit line current does not flow through the cross coupled pair and load devices.